This invention relates to an improvement in a counting process for time-to-digital converting (TDC) circuits used in analog-to-digital converter (ADC) of pulse-height analyzers or time analyzers, and, more particularly, to a counting process for TDC circuits wherein a variation is provided at every conversion cycle between the phases that a scaler is operated by gated clock-pulses. The "scaler" means a scaling circuit. This scaling circuit is used to count the number of pulse signals which are coming into a circuit. The scaling circuit is widely applied for a precise measurement of frequencies or times. A typical example of the scaling circuit is a so-called binary counter circuit or a flip-flop. The interference resulting from the operation of the scaler to the gate circuits and a clock oscillator is eliminated by varying the phases.
In the ADC, digital information is obtained by gating clock-pulses by using time signals and, thereafter, the number of the clock-pulses that are gated is counted over a period where time signals exist. In order to expedite the operation of analysis, high speed clock-pulses are used to accelerate the pulse rate and this results in a tendency to deteriorate the differential non-linearity. Therefore, it is not practically used in the ADC unless the clock rate is extremely limited.
The differential non-linearity is considered to be an important characteristic in pulse-height analyzers etc. and represents the uniformity of analog quantity which is occupied by each digital value.
In a pulse-height analyzers, generally, a histogram is obtained by summing extremely high numbers of values which are obtained from analyses and the analyzers operate to provide finally one output and so an accurate histogram is not obtained unless each digital value assumes theoretically a uniform appearance probability. The differential non-linearity represents the uniformity stated above and the uniformity is an important characteristic in an instrument used for measurement wherein the histogram above stated is obtained. A uniformity at least less than from 1% to 0.5% is required.
The TDC circuits which are employed in the pulse-height analyzers etc. are generally and widely used as one which has, in principle, good differential non-linearity. However, when the pulse rate is accelerated, the operation in the gates becomes incomplete and the operation in the scaler interferes with a clock oscillator or clock gates to provide an odd-even unbalance phenomenon, a 4 channel period unbalance in regularity or an 8 channel period unbalance in regularity and the differential non-linearity is deteriorated with the odd-even unbalance phenomenon left most remarkably. The odd-even unbalance phenomenon is referred to as a phenomenon wherein the digital values are separated into two groups of the odd numbers and the even numbers and unbalance is brought about. The channel is referred to as the digital value itself.
In order to prevent the differential non-linearity which is caused by the unbalance, as stated above, from being deteriorated, the operation of the gate circuits is, in the prior art, made exact as the main countermeasure. In order to make the operation of the gate exact, a synchronizing circuit is generally utilized wherein clock-pulses that are oscillating at an arbitrary phase are gated by time signals incoming at an arbitrary time relation.
An embodiment of the synchronizing gate circuit is shown in FIG. 1. In the figure, clock-pulses generated in a clock oscillator 1 are applied to a gate circuit 3 and, at the same time, time signals coming from an input terminal 2 are also applied to gate circuit 3. The outputs gated at gate circuit 3 are counted at a scaler 4. Gate circuit 3 is comprised of a Type D Flip-Flop (Type D-FF) 5 and an AND gate 9. The time signals are applied to the Type D-FF 5 at a data input terminal (Terminal D) 7 and are synchronized with the clock-pulses applied to the Type D-FF 5 at a clock terminal (Terminal C) 6 to set the Type D-FF 5. The output which is set is obtained at an output terminal (Termianl Q) 8 to gate AND gate 9 by the signals which are obtained through synchronization with the clock-pulses. The clock-pulses coming from clock oscillator 1 are directly applied to one of the input terminals in AND gate 9 and to the other of the input terminals in AND gate 9 are applied the synchronized signals, above stated. According to this construction, the clock-pulses are synchronized with the gate signals in AND gate 9, so the incomplete operation of scaler 4 becomes less and scaler 4 operates exactly.
Further, a gate circuit 17 shown in FIG. 2 may be utilized to double the synchronizing circuit in order to make the synchronizing operation perfect when it is considered that the synchronizing operation is insufficient by the circuit shown in FIG. 1.
The circuit shown in FIG. 1 or FIG. 2 emphasizes the synchronization so that the synchronization can be performed exactly to some extent. However, it is naturally impossible to eliminate fully the incomplete operation of the scaler and the incomplete operation still remains quite slightly.
Further, the odd-even unbalance phenomena, above stated, cannot be improved only by the complete operation of the gate circuit but the following phenomena appear as it is explained in FIG. 3. The 2.sup.0 order 31 or the 2.sup.1 order 33 themselves of a scaler 30 and the signals at output terminals 32 and 34 of scaler 30 are derived, from the operation of the 2.sup.0 order 31 or the 2.sup.1 order 33, directly or indirectly, at a clock oscillator 25, an output terminal 27 of the clock oscillator, a gate circuit 28, an input terminal 26 for the time signals and an output line 29 of the gate circuit etc. to provide an interference at twice or four times periods of the clock-pulses.
For instance, the interference coming from the first stage 2.sup.0 order 31 of scaler 30 and from output terminal 32 of the scaler has a period of twice the period of the clock-pulses and the period of the clock-pulses are repeated alternately at a wide period and at a narrow period every each other, according to the phase wherein the interference is superimposed to the clock-pulses. Therefore, when the interference occurs before gate circuit 28, the odd-even unbalance cannot be avoided with whatever exact operation of the gate circuit utilized and with whatever exact synchronization effected.
The defect, above stated, is left unsettled in the prior art circuits and the clock-pulse rate cannot be expedited due to the odd-even unbalance phenomana.